Job Title: Senior Verification Engineer
Duration: 1+ year W2 contract with
Location: Menlo Park, CA
Verify custom data path IPs used in Computer Vision algorithms.
Develop Test Plans and enhance existing Test Plans.
Implement UVM Test Bench.
Implement test sequences as per plan and debug failures
Identify and implement functional coverage grids and achieve 100 % functional and code coverage.
Run and debug Gate Level Simulations.
Work closely with designers, micro architects & f/w to resolve issues
Ability to communicate & articulate clearly progress / issues with project leads
BS / MS, 3+ years of proven experience as a DV engineer
Hands on experience with SV and UVM
Hands on Experience with executable test plans and Coverage Driven verification
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Familiarity with C/C++
Python (or similar) scripting language
Ten-Silica DSP experience
RISC V experience
Education: BS or MS in Electrical & Electronics or Electronics.
Skills and Experience:
Senior Verification Engineer
Minimum Degree Required: Bachelor's Degree