Design Engineer (ASIC) : 9482290
- Menlo Park, CA
Job Title: Design Engineer
Location: Menlo Park, CA
Duration: 12+ months
Duties:Manage implementation custom ASIC IP and FPGA/Zebu prototype designs
Skills: MINIMUM QUALIFICATIONS
- Co-ordinate between Architectures, Designers and Verification engineers to develop schedules, milestones and tasks.
- Manage and track schedule & tasks using facebook tools.
- Support the IP team in cross functional interaction.
- Assist the program to get synthesis and timing closed on schedule.
- Work with FPGA engineers to align deliverables
- Support activiiteis to handoff and integration of blocks into larger SOC environments
- Assist with Algorithm analysis, verification and improvement
- Contribute to ASIC digital architecture, design and verification
- Ability to document and communicate clearly
- 10+ years of experience as a ASIC Design Engineer
- Experience with program management tools.
- Exposure to IP architecture, Micro-Architecture, RTL coding, verification methodology, Lint/CDC tools, synthesis and LEC tools
Education: BS Electrical Engineering/Computer Science or equivalent experienceRequired Skills: CODINGDESIGN ENGINEERDIGITAL DESIGNENGINEERLEC
- Exposure to HLS coding using Catapult and Xilinx Vivado tools
- Python (or similar) scripting experience
- ASIC design experience
- Masters Degree in EE
APPLICATION-SPECIFIC INTEGRATED CIRCUIT
FIELD PROGRAMMABLE GATE ARRAY
Wednesday, October 16, 2019