Design Engineer (ASIC) : 9482290

Infotech Sourcing - Menlo Park, CA

Job Title: Design Engineer

Location: Menlo Park, CA

Duration: 12+ months

Duties:Manage implementation custom ASIC IP and FPGA/Zebu prototype designs

RESPONSIBILITIES

  • Co-ordinate between Architectures, Designers and Verification engineers to develop schedules, milestones and tasks.
  • Manage and track schedule & tasks using facebook tools.
  • Support the IP team in cross functional interaction.
  • Assist the program to get synthesis and timing closed on schedule.
  • Work with FPGA engineers to align deliverables
  • Support activiiteis to handoff and integration of blocks into larger SOC environments
  • Assist with Algorithm analysis, verification and improvement
  • Contribute to ASIC digital architecture, design and verification
  • Ability to document and communicate clearly
Skills: MINIMUM QUALIFICATIONS
  • 10+ years of experience as a ASIC Design Engineer
  • Experience with program management tools.
  • Exposure to IP architecture, Micro-Architecture, RTL coding, verification methodology, Lint/CDC tools, synthesis and LEC tools
PREFFERED QUALIFICATIONS
  • Exposure to HLS coding using Catapult and Xilinx Vivado tools
  • Python (or similar) scripting experience
  • ASIC design experience
  • Masters Degree in EE
Education: BS Electrical Engineering/Computer Science or equivalent experience

Required Skills:
CODING
DESIGN ENGINEER
DIGITAL DESIGN
ENGINEER
LEC

Additional Skills:
ALGORITHM
ANALOG SILICON
APPLICATION-SPECIFIC INTEGRATED CIRCUIT
ARCHITECTURE
ASIC
ASIC DESIGN
ELECTRICAL ENGINEERING
FIELD PROGRAMMABLE GATE ARRAY
FPGA
INTEGRATION
INTEGRATOR
PROTOTYPE
PROTOTYPING
PYTHON
SCRIPTING
SOC
VERILOG
XILINX



Posted On: Wednesday, October 16, 2019



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