Job Title: Digital Design Engineer
Location: Menlo Park, CA
Duration: 2+ years W2 with possible extension/conversion
Leading social media company
Digital Design Engineer to implement custom logic in ASIC for the company’s AR/VR products and in FPGA for prototyping and research.
Areas of interest include Graphics, Audio or Compression.
Primary language is SystemVerilog with some HLS where it is effective.
Implement and deliver verified RTL blocks given architecture and micro-architecture requirements.
Contribute to the architecture and microarchitecture requirements.
Support the DV, PD, and Firmware teams to ensure correctness of the delivered RTL.
Respond to issues found by engineers running the Lint, CDC, STA, Synthesis, and LEC tools.
Support handoff of RTL blocks to prototyping engineers for integrating the delivered RTL into FPGA platforms.
Key Skill Requirements:
Experience in RTL coding. Preference for SystemVerilog.
Experience with the ASIC development flow from contributing to architecture, through owning micro-architecture and design, to assisting with first bring-up.
Experience solving Lint, CDC, STA, Synthesis, and LEC issues.
Experience with creating clear documentation and communications among and across the teams.
At a high level, describe a recent project you worked on and what your role was on that project.
Can you describe the ASIC flow from Architecture to silicon bring-up?
Can you explain the difference between directed testing and constrained random testing, and when during the design phase they are useful?
What design techniques can be used to reduce power, and which of those do you have experience implementing?
Describe how a bus of signals would be sent from one clock domain to another when the clock domains are asynchronous.
How many flip-flops are required to make a counter that can count up to 15? And up to 63?
How would you make a counter that could be reused for different count sizes?
Posted On: Thursday, May 2, 2019
Compensation: $116 PER HOUR