Current Openings

Design Engineer IV - Digital Design Engineer/ASIC Engineer

Infotech Sourcing - Menlo Park, CA

Job Title: Design Engineer IV

Duration: 12 months under W2

Location: US-CA- Menlo Park

Digital Design Methodology and Release Engineer

RESPONSIBILITIES

• Run and maintain scripts for IP releases, triage issues, and make releases

• Setup Spyglass Lint, CDC, and DFT flows, report status, triage issues, and drive closure

• Setup Synopsys DC elaboration methodology flows, report status, triage issues, and drive closure

• Support handoff and integration of blocks into larger SOC environments

• Ability to document and communicate clearly

MINIMUM QUALIFICATIONS

• 10-12 years of experience as a Digital Design Engineer

• Experience in RTL coding, Spyglass Lint/CDC tools, Synthesis and LEC tools

• Scripting experience (Python or similar languages)

• BS Electrical Engineering/Computer Science or equivalent experience

PREFERRED QUALIFICATIONS

• ASIC design experience

• System Verilog OVM/UVM DV experience

• GIT Version control

• Masters Degree in EE

OPTIONAL PLUS QUALIFICATION

• Implement RTL using HLS and System Verilog

• HLS coding using Catapult and Xilinx Vivado tools

• Experience with Verilog code generators

• Design of Computer Vision Hardware

Top 3 Must have skills:

Being able to run Spyglass tools: Experience in RTL coding, Spyglass Lint/CDC tools, Synthesis and LEC tools

Write Python Scripts

GIT experience



Posted On: Thursday, May 13, 2021



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