Design Verification Engineer

Infotech Sourcing - Menlo Park, CA

Job Title: Design Verification Engineer

Location: Menlo Park, CA or Redmond, WA

Duration: 1+ year W2 contract with possible extension/conversion

Leading social media company

Responsibilities:


  • Write and augment existing test plans.

  • Implement testbench and scoreboards / checkers.

  • Implement test sequences as per plan and debug failures

  • Achieve 100% functional and code coverage

  • Work closely with designers, micro architects & f/w to resolve issues

  • Ability to communicate & articulate clearly progress / issues with project leads

Minimum Qualifications:


  • 5+ years of proven experience as a DV engineer

  • Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology - standardized methodology for verifying integrated circuit designs)

  • Hands on Experience with executable test plans and Coverage Driven verification

  • Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools

  • Familiarity with C/C++

Required Skills:

  • ARTICULATE

  • ENGINEER

  • TEST PLANS

  • APPLICATION-SPECIFIC INTEGRATED CIRCUIT

  • ASIC

Preferred Qualifications:


  • Python (or similar) scripting language

  • ASIC design experience

  • Experience in DSP based Audio or Computer Graphics or Compression' is desirable

  • C++

  • CADENCE

  • DEBUG

  • SYNOPSYS



Posted On: Thursday, May 2, 2019
Compensation: $117/HR



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