Job Title: Technical Program Manager IV
Duration: 12 months W2 ( possible conversion)
Location: Menlo Park, CA
Serve as the primary point of accountability managing development of critical custom IPs with complex cross-functional dependencies across silicon, FW, power and perf teams.
Develop IP intercept schedules, identify critical paths, resolve bottlenecks and drive on-time execution throughout the duration of programs.
Ensure parallel development of FW/SW for relevant IP block(s).
Ensure IP-related documentation is complete, current and available for staff and leadership review.
Establish best practices and technology development processes in a quickly-changing and dynamic environment to ensure on-time delivery.
Build and maintain strong working relationships across Silicon engineering and cross-functional product leadership, and effectively communicate program status to key stakeholders and management.
Drive on-time design, development and delivery of pre-silicon development vehicles including FPGAs.
Contribute to resource planning to ensure program success.
Experience managing development of multiple complex IPs in parallel, each targeting one or more chips and landing concurrently.
Proven experience in managing complex IP development from definition to silicon bring-up, including all stages: architecture, DD, DV, and post-Si debug
Strong sense of urgency and ownership, and execution mind-set
5+ years of experience developing silicon for low-power consumer devices
Deep familiarity with silicon design and development process
Prefer experience in building pixel-processing IPs and sub-systems (GPU or CV IPs)
Top non-negotiable must haves on a resume
ASIC and or Silicon IP Development experience
>5 years of ASIC Program management experience
BS in Engineering