Lead Project Engineer

LaBine & Associates - Santa Clara, CA

Unique opportunity to join an established international company in its US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Lead Project Engineer will be a key person in this growing leader in ASIC, SoC, and ASSPs.

This is a technical position, working closely with verification and ASIC development teams as well as customers. The selected candidate will lead and drive projects, provide technical leadership, and make sure the team delivers final silicon designs from R&D to the customer. Must have extensive experience in an SoC organization, ASIC design and verification knowledge, the ability to perform some hands-on verification activities, and a track record of delivering silicon solutions.

Primary Responsibilities Include:

  • Lead Projects that are currently in the advanced stages of the sales pipeline.
  • Work and liaison with other Design & Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action.
  • In-Depth knowledge of Design & Verification and be able to provide feedback to the design team.
  • Work closely with the design team to ensure the Company is meeting design requirements for projects. This may include a review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benches.
  • Work closely with the Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage, and drive timely and accurate deliverables with customers within schedules.
  • Will be part of a team delivering silicon solutions to some of the biggest brands in the world.


    Qualifications | Required:

  • BS or MS in Computer Science or Electrical Engineering.
  • 8-15 years in an SoC Organization.
  • Functional understanding of constrained random verification (UVM), functional coverage, and code coverage.
  • Functional understanding of clock domain crossings, lint/CDC checks, SDC, leading protocols such as PCIe, USB, MIPI, experience with embedded CPUs.

Posted On: Monday, June 1, 2020

Position Contact
Laura LaBine
Chief Talent Officer
(650) 393-3161
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